1. Field of the Invention
The present invention relates to a switching regulator and in particular to a switching regulator that eliminates the right half-plane zero phenomenon.
2. Related Art
Switching regulators typically include a pulse-width modulation (PWM) circuit running at a fixed frequency. FIG. 1A illustrates a conventional switching regulator 100 including a comparator 111 that drives a switch 119, e.g. a large NMOS or NPN device, wherein comparator 111 and switch 119 implement the PWM circuit. When switch 119 is “on” (called a charge time), an inductor 109 is charged, thereby causing the current in inductor 109 to increase. In contrast, when switch 119 is “off” (called a discharge time), inductor 109 supplies current/voltage to an output node 115 via a diode 116.
Notably, adjusting the duty cycle of the PWM circuit, i.e. the ratio of the “on” time of switch 119 divided by its period (“on” i+“off” time), can control the voltage/current supplied to output node 115. To adjust the duty cycle, switching regulator 100 can provide a feedback signal VFBK from output node 115 to a negative input terminal of an error amplifier 102 (e.g. a gm stage). Error amplifier 102 compares feedback signal VFBK to a known feedback reference 101 (voltage/current), which is provided on its positive input terminal. If feedback signal VFBK is less than feedback reference 101, thereby indicating that more output voltage/current is required, then error amplifier 102 drives an error signal VERROR higher using a parasitic element 103 (which represents the output impedance of error amplifier 102), a compensation zero resistor 104, and a compensation capacitor 105 (wherein parasitic element 103, compensation zero resistor 104, and compensation capacitor 105 result in a compensation time constant that can provide circuit stability).
Comparator 111 receives error signal VERROR on its negative input terminal and a ramping signal VRAMP on its positive input terminal. A higher error signal VERROR relative to ramping signal VRAMP causes comparator 111 to turn on transistor 119 longer, thereby increasing the duty cycle of the PWM circuit. The increased duty cycle, in turn causes the charge time of inductor 109 to be increased, thereby ultimately resulting in a higher output voltage/current during discharge time.
In this embodiment, ramp generator 120 includes a comparator 112, a transistor 114, and a capacitor 113. Comparator 112 drives a transistor 114, which is connected between ground and a positive input terminal of comparator 112. Capacitor 113 is connected between ground VSS and the positive input terminal of comparator 112. Current source 110 is connected between a voltage source VDD and the positive input terminal of comparator 112. Inductor 109 is connected between diode 116 and a node between voltage VDD and current source 110. Comparator 112 compares the current/voltage on its positive input terminal to a ramp reference (current/voltage) 107.
In this configuration, comparator 112 operates by allowing capacitor 113 to charge via current source 110 until a ramp signal VRAMP reaches a reference voltage VRREF, which is generated by ramp reference 107. At this point, the output of comparator 112 switches high, thereby turning on transistor 114 and discharging capacitor 113 to start the next cycle. Note that comparator 112 typically has sufficient hysteresis to guarantee that capacitor 113 is fully discharged on each cycle. Thus, ramp generator 120 operates as an oscillator that generates a ramp waveform 121 (corresponding to ramp signal VRAMP), shown in FIG. 1B. Ramp waveform 121 has an associated charge time 122 (i.e. associated with turning on switch 119 and charging inductor 109) and an associated discharge portion 123 (i.e. associated with turning off switch 119 and discharging inductor 109). In a first cycle of ramp waveform 121, the duty cycle of the PWM circuit is 50% (i.e. the on/off times of switch 119 are equal).
In actual operation, an external load 118 connected to output node 115 can vary. For example, a load 118 including 2 “on” LEDs could change to have 4 “on” LEDs. In this case, the feedback loop should respond by increasing the duty cycle to generate more output to compensate for the additional load. To increase the duty cycle, the charge time is increased (i.e. switch 119 is turned on longer). However, a necessary side effect of increasing the charge time is a decrease in the corresponding discharge time in the cycle. That is, in waveform 121, a charge time 124 would be increased relative to a discharge time 125, but the period remains the same. Because current is supplied to output node 115 only during the discharge time, there is an instantaneous drop in output current/voltage whenever the feedback loop asks for more output. Within one or more cycles, the increase in the charge time (e.g. charge time 124) ramps up the current in inductor 109 enough to overcome that instantaneous drop, thereby allowing the output voltage/current to rise.
A signal processing system that exhibits this initial negative response (i.e. wanting more output, but actually getting less) resolving to a final positive output (i.e. wanting more output, and actually getting more) has what is known as a right half-plane zero (RHPZ) (this means that in the Laplace Domain, an (s-a) term exists in the numerator). The RHPZ is a well-known effect in many switching regulators that causes difficulties in stabilizing the feedback loop. Because the RHPZ problem stems from the initial inversion of the error signal as the switching regulator is correcting for a disturbance, i.e. a load increase. Typically, the solution is to slow switching regulator 100 sufficiently by incorporating a larger compensation capacitor 105 so that the inversion does not cause stability problems. Unfortunately, a larger compensation capacitor results in slower response time, thereby degrading performance of switching regulator 100.